Field of the Invention
The present invention is generally related to processing packets of data. More specifically the present invention is related to optimizing the performance of processing a plurality of data packets.
Description of the Related Art
Computer systems commonly process packets that may be received over a computer network. When packets are received at a computer system that includes a multi-core processor the packets are typically assigned to a processing core at the multi-core processor randomly for processing. In certain instances each processing core of a multi-core processor accesses a private or semi-private level 1 (L1) cache when processing packets.
When the L1 cache of a processor does not contain instructions that enable it to process a packet (a cache miss), that processor will typically access a level 2 (L2) cache or another memory to fetch program code required to process the packet. Since the L1 cache is significantly faster than an L2 cache or other memory, the processing of packets slows down as soon as a processor identifies that it must access the L2 cache or other memory. Conventional multi-core processing systems frequently will share an L2 cache or other memories with a plurality of processor at the multi-core processing system.
Since a processor accessing program code from an L2 cache or other memory is slow, the performance of a multi-core processing system slows down whenever a processor access the L2 cache or other memory as compared to the instance where the processor need only access an L1 cache that is associated with the processor. Frequently memories contained within an L1 cache are expensive because they are often very high speed memories. Since L1 caches commonly include expensive memories the amount (i.e. size/storage capacity) of the L1 cache is frequently limited.
What is needed to maximize the performance of a processing core processing packets is a system and a method by which a processor may access its associated local L1 cache with an increased cache hit rate.